Embedded memories may consume 50% or more of a die area, which is expected to increase in the coming years. New models are being generated to test algorithms or procedures on the memory units. Various systems have been designed which facilitate a designer to determine a location of insertion for memory built-in self-test (“MBIST”) logic. However, this information is generally not available at the register transfer level (“RTL”). Some information regarding the location of the MBIST logic may be provided to a designer in a post elaborated version (e.g., in VHSIC Hardware Description Language (“VHDL”) or Verilog using primitive gates), however, this info is not sufficient to modify existing MBIST logic.
When designing a memory, or during the chip-design process, designers will insert the MBIST logic. After MBIST logic insertion, designers may make changes to the RTL. These changes to the RTL may affect the MBIST logic, yet the designers are generally unaware of how their changes to the RTL may affect the MBIST logic and cannot modify an existing MBIST logic. In order to account for changes to the RTL, previously, designers would have to revert back to a design that did not include the MBIST logic in order to locate the MBIST logic. However, the current design that resulted in changes needing to be made to the MBIST logic may be so far removed from the original design without the MBIST logic, that this is not preferable, as a significant amount of time may be lost.
Other methods for accounting for changes to MBIST logic include using a strategy that compares the current design with the MBIST logic that needs to be replaced to a design with new MBIST logic in order to generate a change list for the current design with the MBIST logic that needs to be replaced. This, however, is a difficult task, and is generally avoided.
Thus, it may be beneficial to provide an exemplary system, method, and computer-accessible medium for register-transfer level design engineering, which may overcome at least some of the deficiencies presented herein above.